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| PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's FEATURES * * * * * * * * * * Selectable 750kHz to 800MHz range. Low phase noise output (@ 10kHz frequency offset, -142dBc/Hz for 19.44MHz, -125dBc/Hz for 155.52MHz, -115dBc/Hz for 622.08MHz). CMOS (PLL502-37), PECL (PLL502-35 and PLL502-38) or LVDS (PLL502-39) output. 12 to 25MHz crystal input. No external load capacitor or varicap required. Output Enable selector. Wide pull range (+/-200 ppm) Selectable 1/16 to 32x frequency multiplier. 3.3V operation. Available in 16-Pin (TSSOP or 3x3mm QFN). PIN CONFIGURATION (Top View) VDD XIN XOUT SEL3^ SEL2^ OE VCON GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 SEL0^ SEL1^ GND CLKC VDD CLKT GND GND The PLL502-35 (PECL with inverted OE), PLL502-37 (CMOS), PLL502-38 (PECL), and PLL502-39 (LVDS) are high performance and low phase noise VCXO IC chips. They provide phase noise performance as low as -125dBc at 10kHz offset (at 155MHz), by multiplying the input crystal frequency up to 32x. The wide pull range (+/- 200 ppm) and very low jitter make them ideal for a wide range of applications, including SONET/SDH and FEC. They accept fundamental parallel resonant mode crystals from 12 to 25MHz. XOUT SEL3^ SEL2^ OE 13 14 15 16 12 11 10 SEL1^ 9 DESCRIPTION XIN SEL0^ / VDD* VDD / GND* P502-3x 1 2 3 4 PLL 502-3x GND GND 8 7 6 5 GND CLKC VDD CLKT VCON BLOCK DIAGRAM SEL OE Vin X+ XOscillator Amplifier w/ integrated varicaps PLL (Phase Locked Loop) ^: *: Internal pull-up On 3x3 package, PLL502-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PLL502-37/-39 have SEL0 (pin 10), and pin11 is VDD. See pin assignment table for details. OUTPUT ENABLE LOGICAL LEVELS Part # PLL502-38 PLL502-35 PLL502-37 PLL502-39 OE 0 (Default) 1 0 1 (Default) Tri-state Tri-state GND State Output enabled Q Q Output enabled PLL by-pass PLL502-3x OE input: Logical states defined by PECL levels for PLL502-38 Logical states defined by CMOS levels for PLL502-37/-39 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 1 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's FREQUENCY SELECTION TABLE SEL3 0 0 0 1 1 1 1 1 1 1 SEL2 0 1 1 0 0 0 1 1 1 1 SEL1 1 1 1 0 1 1 0 0 1 1 SEL0 1 0 1 1 0 1 0 1 0 1 Selected Multiplier Fin x 32 Fin / 8 Fin x 2 Fin / 2 Fin / 16 Fin x 4 Fin / 4 Fin x 8 Fin x 16 No multiplication Note: SEL0 is not available (always "1") for PLL502-35 and PLL502-38 in 3x3mm package PIN DESCRIPTIONS PLL502-35 and PLL502-38 (see next page of PLL502-37/-39) Name XIN XOUT OE VCON GND CLKT CLKC SEL0 SEL1 SEL2 SEL3 VDD TSSOP Pin number 2 3 6 7 8,9,10,14 11 13 16 15 5 4 1, 12 3x3mm QFN Pin number 12 13 16 1 2,3,4,8,11 5 7 Not available 9 15 14 6,10 Type I I I I P O O I I I I P Description Crystal input. See Crystal Specification on page 4. Crystal output. See Crystal Specification on page 4. Output enable pin (see OE logic state table on page 1). Voltage Control input. Ground. True output PECL Complementary output PECL. Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. +3.3V power supply. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 2 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's PIN DESCRIPTIONS PLL502-37/-39 (see previous page of PLL502-35/-38) Name XIN XOUT OE VCON GND CLKT CLKC SEL0 SEL1 SEL2 SEL3 VDD TSSOP Pin number 2 3 6 7 8,9,10,14 11 13 16 15 5 4 1, 12 3x3mm QFN Pin number 12 13 16 1 2,3,4,8 5 7 10 9 15 14 6,11 Type I I I I P O O I I I I P Description Crystal input. See Crystal Specification on page 4. Crystal output. See Crystal Specification on page 4. Output enable pin (see OE logic state table on page 1). Voltage Control input. Ground. True output LVDS (PLL502-39) (N/C for PLL502-37) Complementary output LVDS (PLL502-39) (CMOS out for PLL502-37). Multiplier selector pins. These pins have an internal pull-up that will default SEL to `1' when not connected to GND. +3.3V power supply. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 2 UNITS V V V C C C C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 3 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR SYMBOL FXIN CL (xtal) C0/C1 (xtal) RE CONDITIONS Parallel Fundamental Mode At VCON = 1.65V AT cut AT cut MIN. 12 TYP. 9.5 MAX. 25 250 30 UNITS MHz pF Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nominal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW SYMBOL TVCXOSTB CONDITIONS From power valid FXIN = 12 - 25MHz; XTAL C0/C1 < 250 0V VCON 3.3V VCON=1.65V, 1.65V MIN. TYP. MAX. 10 UNITS ms ppm ppm ppm/V % k kHz 500 200 150 10 2000 25 0V VCON 3.3V, -3dB Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current SYMBOL IDD VDD CONDITIONS PECL/LVDS/CMOS Fout<24MHz 24MHz TYP. MAX. 60/28/15 65/45/30 100/80/40 3.63 55 55 55 UNITS mA V % mA 2.97 @ 50% VDD (CMOS) @ 1.25V (LVDS) @ V DD - 1.3V (PECL) 45 45 45 50 50 50 50 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 4 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's 5. Jitter Specifications PARAMETERS CONDITIONS With capacitive decoupling between VDD and GND. Over 10,000 cycles. FREQUENCY 19.44MHz 77.76MHz 155.52MHz 622.08MHz 19.44MHz 77.76MHz 155.52MHz 622.08MHz 155.52MHz 622.08MHz MIN. TYP. 2.2 4.5 4.5 5.0 17 25 27 35 2.5 2.5 MAX. UNITS Period jitter RMS ps Period jitter Peak-toPeak 1 With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz ps Integrated jitter RMS 2 4 4 ps 6. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier (typical) FREQUENCY 19.44MHz 77.76MHz 155.52MHz 622.08MHz @10Hz -80 -72 -65 -55 @100Hz -108 -103 -95 -85 @1kHz -132 -122 -120 -109 @10kHz -142 -130 -125 -115 @100kHz -150 -125 -121 -110 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V 7. CMOS Electrical Characteristics PARAMETERS Output drive current Output Clock Rise/Fall Time SYMBOL IOH IOL CONDITIONS VOH= VDD-0.4V, VDD=3.3V VOL = 0.4V, VDD = 3.3V 0.3V ~ 3.0V with 15 pF load MIN. 10 10 TYP. MAX. UNITS mA mA ns 2.4 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 5 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's 8. LVDS Electrical Characteristics PARAMETERS Output Differential Voltage VDD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change Power-off Leakage Output Short Circuit Current SYMBOL VOD VOD VOH VOL VOS VOS IOXD IOSD CONDITIONS MIN. 247 -50 TYP. 355 MAX. 454 50 UNITS mV mV V V V mV uA mA RL = 100 (see figure) 1.4 0.9 1.125 0 1.1 1.2 3 1 -5.7 1.6 1.375 25 10 -8 Vout = VDD or GND VDD = 0V 9. LVDS Switching Characteristics PARAMETERS Differential Clock Rise Time Differential Clock Fall Time LVDS Levels Test Circuit OUT SYMBOL tr tf CONDITIONS C L = 10 pF (see figure) RL = 100 MIN. 0.2 0.2 TYP. 0.7 0.7 MAX. 1.0 1.0 UNITS ns ns LVDS Switching Test Circuit OUT 50 CL = 10pF VOD VOS VDIFF RL = 100 50 CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 20% 0V 80% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 6 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's 10. PECL Electrical Characteristics PARAMETERS Output High Voltage Output Low Voltage SYMBOL VOH VOL CONDITIONS RL = 50 to (VDD - 2V) (see figure) MIN. VDD - 1.025 MAX. VDD - 1.620 UNITS V V 11. PECL Switching Characteristics PARAMETERS Clock Rise Time Clock Fall Time SYMBOL tr tf CONDITIONS 20%~80% of Waveform 20%~80% of Waveform MIN. TYP. 0.6 0.6 MAX. 1.5 1.5 UNITS ns ns PECL Levels Test Circuit OUT VDD OUT PECL Output Skew 50 2.0V 50% 50 OUT OUT tSKEW PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 7 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's PACKAGE INFORMATION 16 Pin TSSOP Dimensions in ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 e B C L 16 Pin 3x3 QFN D A A A E e L b Symbol A A1 b D E e L Dimension in MM Min. Max. 0.70 0.80 0.203 REF 0.18 0.30 2.90 3.10 2.90 3.10 0.50 BSC 0.30 0.50 Dimension in inch Min. Max. 0.028 0.032 0.008 REF 0.007 0.012 0.114 0.122 0.114 0.122 0.020 BSC 0.012 0.020 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 8 PLL502-35/-37/-38/-39 750kHz - 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC's ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type, Operating temperature range, shipping method PLL502-3x X X X -R PART NUMBER NONE= TUBE -R=TAPE AND REEL NONE=NORMAL PACKAGE L=GREEN PACKAGE TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE O=TSSOP Q=QFN Order Number PLL502-35OC PLL502-35OC-R PLL502-35QC PLL502-35QC-R PLL502-35OCL PLL502-35OCL-R PLL502-35QCL PLL502-35QCL-R PLL502-37OC PLL502-37OC-R PLL502-37QC PLL502-37QC-R PLL502-37OCL PLL502-37OCL-R PLL502-37QCL PLL502-37QCL-R PLL502-38OC PLL502-38OC-R PLL502-38QC PLL502-38QC-R PLL502-38OCL PLL502-38OCL-R PLL502-38QCL PLL502-38QCL-R PLL502-39OC PLL502-39OC-R PLL502-39QC PLL502-39QC-R PLL502-39OCL PLL502-39OCL-R PLL502-39QCL PLL502-39QCL-R Marking P502-35OC P502-35OC P502-35QC P502-35QC P502-35OCL P502-35OCL P502-35QCL P502-35QCL P502-37OC P502-37OC P502-37QC P502-37QC P502-37OCL P502-37OCL P502-37QCL P502-37QCL P502-38OC P502-38OC P502-38QC P502-38QC P502-38OCL P502-38OCL P502-38QCL P502-38QCL P502-39OC P502-39OC P502-39QC P502-39QC P502-39OCL P502-39OCL P502-39QCL P502-39QCL Package Option 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin 16-Pin TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) TSSOP (Tube) TSSOP (Tape and Reel) 3x3 QFN (Tube) 3x3 QFN (Tape and Reel) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 9 |
Price & Availability of P502-39QCL
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